1. Field of the Invention
The present invention relates to Random Access Memory with a plurality of symmetrical memory cells which are connected in groups to complementary bit lines, which complementary bit lines are coupled through a cross coupled device.
2. Background of the Invention
A memory may include a plurality of symmetrical Random Access Memory (SRAM) cells arranged in columns and rows. Each SRAM cell may store a bit of data. To read a value stored in a cell or to write a value into a cell, a column including the cell may be selected, and a row including the cell may be selected.
Symmetrical memory cells as they are used in SRAMs are built up with two nodes wherein each node is connected to one line of a pair of a complementary bit line. FIG. 1 shows such a well known and common architecture. The memory cell 2 is connected with its two nodes tru and cmp to a complementary bit line with a pair of lines blc and blt for column selection. The row selection signal line is named in this example wl. To avoid faults during read or write processes through effects discussed by FIG. 2 cross coupled devices are used in between the pair of complementary bit line blc and blt. The known cross coupled devices are built up by a pair of transistors 31, 32 that are coupling the pair of bit lines blc and blt in the shown manner.
FIG. 2 explains parasitic effects that occur. On top of FIG. 2 a cell transfer device of an unselected, and therefore switched off, cell is depicted.
Caused by gate impurities from processing or device thresholds close to or below 0 it is possible that conduct leakage occurs at the transfer device 5 of a memory cell connected to the bit line BLT. This leakage is shown as resistor 51. Many closed cells are usually connected to a bit line what adds these negative effects.
The device at the bottom of FIG. 2 depicts a resulting resistor 52 which represents leakage to devices of circuitry connected to bit other than the memory cells.
The device in the middle of FIG. 2 depicts the part of a selected cell (wl=HIGH) which is in a state driving bit high. The transfer device 5 in series with the pull up device 6 has to compensate the leakage shown by arrow 53. At a certain amount of leakage the compensation is not sufficient resulting in that the read signal is too weak. In absence of any cross coupled devices this situation causes yield loss. Though the probability of leakage defects is low the very large amount of memory cells connected to a bit line makes the loss significant and therefore cross coupled devices as shown in FIG. 1 are implemented. They can compensate a large amount of leakage.
As a negative effect cross coupled devices cause disturbances when writing a memory cell.
During write signals, which are distributed by global data lines (i.e. for writing data_c and data_t), it may occur that the complementary bit lines bit and blc are set later than wl selects a cell. This causes the bit lines to be biased like in read operation. The cross coupled devices amplify the unwanted read signal and disturb the write operation when it has to set bit and blc in the opposite direction.
This effect causes that write operations are performed wasting time for security reasons.